Extremely high performance at high voltages





TSMC this week announced a new manufacturing process specifically tailored for high-performance computing (HPC) products. N4X promises to combine the transistor density and design rules of TSMC’s N5 family nodes with the ability to drive extra-high voltage chips for higher frequencies, which will be especially useful for server CPUs and SoCs. Interestingly, TSMC’s N4X may enable higher frequencies than even the company’s next-generation N3 process.

One of the problems caused by the shrinking of transistors is the shrinking of their contacts, which means increased contact resistance and consequent power delivery problems. Different manufacturers use different ways to tackle the contact resistance problem: Intel uses cobalt contacts instead of tungsten contacts, while other manufacturers chose to make contacts using selective tungsten deposition technology. While these methods work perfectly for virtually all types of chips, there are still ways to further improve power delivery for High Performance Computing (HPC) designs, which are relatively immodest about the total power/voltage used. This is exactly what TSMC did with its N4X node. But before we go into details about the new manufacturing process, let’s see what benefits TSMC promises with it.

TSMC claims that its N4X node can make up to 15% higher clocks compared to a comparable circuit made with N5, as well as an up to 4% higher frequency compared to an IC produced using its N4P node while operates at 1.2 V. In addition – and seemingly more importantly – the N4X can reach drive voltages in excess of 1.2 V to get even higher clocks. To put the numbers in context, Apple’s M1 family SoCs made on N5 run at 3.20 GHz, but if these SoCs were produced with N4X, then using TSMC’s math, they would theoretically run at about 3.70 GHz. can be pushed or at an even higher frequency at voltages above 1.2V.

TSMC does not compare the transistor density of N4X with other members of its N5 family, but normally processors and SoCs for HPC applications are not designed with high density libraries. In terms of power, drive voltages above 1.2 V will of course increase power consumption compared to chips produced with other N5 class nodes, but since the node is designed for HPC/data center applications, the focus is on delivering the highest possible performance with power supply. a secondary concern. In fact, overall power consumption has increased over the past generations on HPC-class GPUs and similar parts, and there’s no sign that this will stop in the next generations of products, thanks in part to N4X.

“HPC is now TSMC’s fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ line of our high-performance semiconductor technologies,” said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. “The demands of the HPC segment are relentless, and TSMC has not only adapted our ‘X’ semiconductor technologies to unleash ultimate performance, but also combined them with our 3DFabric advanced packaging technologies to provide the best HPC platform.”

Advertised PPA Enhancements of New Process Technologies
Data announced during conference calls, events, press conferences and press releases
TSMC
N5
vs
N7
N5P
vs
N5
N5HPC
vs
N5
N4
vs
N5
N4P
vs
N5
N4P
vs
N4
N4X
vs
N5
N4X
vs
N4P
N3
vs
N5
Current -30% -10% ? lower -22% ? ? -25-30%
Performance +15% +5% +7% higher +11% +6% +15%
or
Lake
+4%
or more
+10-15%
Logical area

Decrease %

(Thickness)

0.55x

-45%

(1.8x)

0.94x

-6%

1.06x

0.94x

-6%

1.06x

?

?

0.58x

-42%

(1.7x)

Volume
production
2nd quarter 2020 2021 Q2 2022 2022 2023 H2 2022 H1
2024?
H1 2024? H2 2022

To improve performance and enable drive voltages in excess of 1.2 V, TSMC had to evolve the entire process stack.

  • First, it has redesigned and optimized its FinFET transistors for both high clock speeds and high drive currents, which likely means reducing resistance and parasitic capacitance and increasing current through the channel. We don’t know if it was supposed to increase the gap between gates and gates and at the moment TSMC doesn’t say what exactly it did and how it affected the transistor density.
  • Second, it introduced new high-density metal-insulator-metal (MiM) capacitors for stable power delivery under extreme loads.
  • Third, it redesigned the back-end-of-line metal stack to provide more power to transistors. Again, we don’t know how this affected the transistor density and ultimately the size of the die.

Intel has largely introduced similar improvements to its 10nm Enhanced SuperFin (now called Intel 7) process technology, which is not surprising as these are natural methods of increasing frequency potential.

What’s spectacular is how significantly TSMC managed to increase the clock speed potential of its N5 technology over time. A 15% increase brings N4X close to its next-generation N3 manufacturing technology. Meanwhile, with drive voltages above 1.2 V, this node will allow for higher clocks than N3, making it particularly good for data center CPUs.

TSMC says it expects the first N4X designs to go into risk production in the first half of 2023, which is a very vague description of timing as it could mean very late 2022 or early 2023. In any case, it usually takes a chip a year to move from risk manufacturing to high volume iteration, so it’s reasonable to expect the first N4X designs to hit the market in early 2024. This is perhaps a weak point of N4X, as by the time the N3 promises to be fully N4X ahead in terms of clocks, N3 will have a big advantage in terms of transistor density.

Source: TSMC




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