Delivers 64 GT/s performance for next-gen data centers with PAM4 signaling

Rambus has just announced its brand new PCIe 6.0 controller that will utilize PAM4 signaling and provide up to 64 GT/s transfer speeds on next-gen data centers. The new controller is fully compliant with PCI-SIG’s PCIe 6.0 specifications released earlier this month.

Rambus PCIe 6.0 Controller Announced: PAM4 Signaling and 64GT/s Transfer Rates for Next-Gen Data Centers

Press release: Rambus Inc, a leading chip and silicon IP provider making data faster and more secure, today announced the availability of its PCI Express (PCIe) 6.0 controller. The PCIe specification is the connection of choice in a broad landscape of data-intensive markets, including data center, AI/ML, HPC, automotive, IoT, defense and aerospace.

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The Rambus PCIe 6.0 controller is optimized for power, area and latency, delivering data rates of up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors PCIe links and protects against physical attacks.

“The rapid advancement of AI/ML and data-intensive workloads requires us to continue to provide higher data rate solutions with best-in-class latency, power and surface area”

“The rapid advancement of AI/ML and data-intensive workloads requires us to continue to deliver faster data-rate solutions with best-in-class latency, power and surface area,” said Sean Fan, chief operating officer at Rambus. “As the latest addition to our portfolio of industry-leading IP interfaces, our PCIe 6.0 controller provides customers with an easy-to-integrate solution that delivers both performance and security for advanced SoCs and FPGAs.”

The main features of the Rambus PCIe 6.0 controller are:

  • Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
  • Supports fixed format FLITs that enable high bandwidth efficiency
  • Implements low-latency Forward Error Correction (FEC) for link robustness
  • The internal data path size is automatically scaled up or down (256, 512, 1024 bits) based on max link speed and width for fewer ports and optimal throughput
  • Backwards compatible with PCIe 5.0, 4.0 and 3.0/3.1
  • Supports endpoint, root port, dual mode and switch port configurations
  • Integrated IDE optimized for performance

PCIe 6.0 delivers transfer speeds of 64 GT/s, twice the data rates compared to PCIe 5.0

How the PCIe 6.0 controller works

The PCIe 6.0 controller is backward compatible with PCIe 5.0, 4.0, and 3.1/3.0 specifications. It supports version 6.x of the PHY Interface for PCI Express (PIPE) specification. The controller provides a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to meet a variety of customer and industry usage scenarios, the IP address can be configured to support endpoint, root port, switch port, and dual-mode topologies, enabling a variety of usage models. The included Graphical User Interface (GUI) Wizard allows designers to fine-tune the IP address to their exact requirements by enabling, disabling and customizing a variety of parameters.

PCI Express layer

  • Designed for the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE 6.x (8, 16, 32 , 64 and 128-bit) specifications
  • Supports SerDes architecture PIPE 10b/20b/40b/80b width
  • Supports original PIPE 8b/16b/32b/64b/128b width
  • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) specification
  • Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
  • Supports endpoint, root port, dual mode, switch port configurations
  • Supports PCIe 6.0 to PCIe 1.0 speeds
  • Supports Forward Error Correction (FEC) – Lightweight, low-latency algorithm
  • Supports L0p Low Power Mode
  • Up to 4-bit parity protection for data path
  • Supports Clock Gating and Power Gating
  • Remote access features include override LTSSM timers, override ACK/NAK/Replay/UpdateFC timers, unencrypted access to the PIPE interface, error injection on Rx and Tx paths, detailed recovery status, and much more, enabling a secure and enabling reliable implementation of IP in mission-critical SoCs

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