Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack


  • Integrity 3D-IC is Cadence’s next-generation multi-chip design solution, integrating silicon and packet planning and deployment with system analysis and sign-off to enable system-driven PPA optimization

  • Native 3D partition flow automates intelligent creation of memory-on-logical 3D stack configuration, bringing PPA enhancements to 3D stack designs

  • Customers can confidently leverage Samsung Foundry’s Cadence Integrity 3D IC platform and multi-die deployment flow to create next-generation hyperscale computing, mobile, automotive and AI applications

SAN JOSE, California, November 17, 2021–(BUSINESS WIRE)–Cadence Design Systems, Inc. (Nasdaq: CDNS), a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE), today announced that Samsung Foundry has qualified the Cadence® Integrity The 2D-to-3D native 3D partition flow of the 3D IC platform. Using the new flow, customers can break existing 2D designs into 3D memory-by-logic configurations and achieve better power, performance and area (PPA) with a homogeneous 3D stack compared to the original 2D design. The flow also provides robust 3D IC system planning, implementation and early analysis capabilities for the partitioned design, ideal for customers creating complex next-generation hyperscale computing, mobile, automotive and AI applications.

If you hit a memory wall where RAM access can’t keep up with CPU execution speed, the overall system slows down due to memory latency. One way to overcome this is to place memories on top of the logic in a homogeneous stack configuration. The configuration, when mounted on the same package, reduces wire length and area and speeds up memory access, improving CPU core performance.

The 3D partitioning of the Integrity 3D IC platform allows the user to separate memory macros and standard cells and place them on two different dies within a homogeneous 3D stack. The automated flow performs partitioning and full implementation of the 3D stack, while creating connections between the macros and default cells. Once the content of each mold is finalized, the system and package can be implemented in the Integrity 3D IC platform, enabling bump planning, implementation, co-design with other molds and early analysis of thermal, power and static timing analysis (STA ).

“Customers facing various automated partitioning requirements for 3D IC configurations can take advantage of this unique capability in Samsung Foundry’s MDI reference stream based on Native 3D partitioning in Cadence’s new Integrity 3D IC platform to minimize the effects of to investigate chip stacking,” said Sangyun. Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “This successful partnership between Cadence and Samsung provides customers with a partitioning, implementation and analysis flow for 3D stacked designs that will help them reduce power consumption and footprint while improving overall system performance.”

“Through our continued partnership with Samsung Foundry, we have collaborated to innovate in multi-die deployment and deliver automated Native 3D partition flows,” said Vivek Mishra, corporate vice president, Product Engineering in the Digital & Signoff Group at Cadence . “Samsung Foundry’s advanced packaging for multi-die deployment, combined with Cadence’s unified Integrity 3D IC platform, provides our mutual customers with robust multi-die solutions.”

The Integrity 3D-IC platform provides customers with a common cockpit and database, a complete planning system, seamless integration of implementation tools, integrated system-level analytics, and an easy-to-use interface, and lets users co-design with the Virtuoso® Design Environment and Allegro® packaging technologies. The platform also includes a broader portfolio of Cadence 3D IC solutions, including the Voltus IC Power Integrity Solution for Power Delivery Network (PDN) Analytics, CelsiusThermal Solver for 3D Thermal Analysis, Tempus Timing Signoff Solution for 3D signoff timing and Pegasus System layout versus schema (LVS) verification system. For more information about the Integrity 3D IC platform, visit

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